This invention relates to dynamic random access memory (xe2x80x9cDRAMxe2x80x9d) devices, and more particularly to refreshing the memory cells of a DRAM in a manner that minimizes the power consumed by the DRAM during a self-refresh mode of operation.
Dynamic Random Access memories (xe2x80x9cDRAMsxe2x80x9d) are commonly used in a variety of electronic devices, such as computers. A high level block diagram of a typical DRAM is shown in FIG. 1. The DRAM shown in FIG. 1 is a synchronous dynamic random access memory (xe2x80x9cSDRAMxe2x80x9d) 10, although the principles described herein are applicable to any memory device containing memory cells that must be refreshed. The SDRAM 10 includes an address register 12 that receives either a row address or a column address on an address bus 14. The address bus 14 is generally coupled to a memory controller (not shown in FIG. 1). Typically, a row address is initially received by the address register 12 and applied to a row address multiplexer 18. The row address multiplexer 18 couples the row address to a number of components associated with either of two memory banks 20, 22 depending upon the state of a bank address bit forming part of the row address. Associated with each of the memory banks 20, 22 is a respective row address latch 26 which stores the row address, and a row decoder 28 which applies various signals to its respective array 20 or 22 as a function of the stored row address. The row address multiplexer 18 also couples row addresses to the row address latches 26 for the purpose of refreshing the memory cells in the arrays 20, 22. The row addresses are generated for refresh purposes by a refresh controller 30 that normally includes a refresh counter (not shown in FIG. 1).
After the row address has been applied to the address register 12 and stored in one of the row address latches 26, a column address is applied to the address register 12. The address register 12 couples the column address to a column address latch 40. Depending on the operating mode of the SDRAM 10, the column address is either coupled through a burst counter 42 to a column address buffer 44, or to the burst counter 42 which applies a sequence of column addresses to the column address buffer 44 starting at the column address output by the address register 12. In either case, the column address buffer 44 applies a column address to a column decoder 48 which applies various signals to respective sense amplifiers and associated column circuitry 50, 52 for the respective arrays 20, 22.
Data to be read from one of the arrays 20, 22 is coupled to the column circuitry 50, 52 for one of the arrays 20, 22, respectively. The data is then coupled to a data output register 56, which applies the data to a data bus 58. Data to be written to one of the arrays 20, 22 are coupled from the data bus 58 through a data input register 60 to the column circuitry 50, 52 where it is transferred to one of the arrays 20, 22, respectively. A mask register 64 may be used to selectively alter the flow of data into and out of the column circuitry 50, 52, such as by selectively masking data to be written to the arrays 20, 22.
The above-described operation of the SDRAM 10 is controlled by a command decoder 68 responsive to high level command signals received on a control bus 70. These high level command signals, which are typically generated by a memory controller (not shown in FIG. 1), are a clock enable signal CKE*, a clock signal CLK, a chip select signal CS*, a write enable signal WE*, a row address strobe signal RAS*, and a column address strobe signal CAS*, which the xe2x80x9c*xe2x80x9d designating the signal as active low. The command decoder 68 generates a sequence of command signals responsive to the high level command signals to carry out the function (e.g., a read or a write) designated by each of the high level command signals. For example, driving the RAS* and CAS* inputs low with CKE* high will cause the SDRAM 10 to enter a self refresh mode. In the self refresh mode, the refresh controller 30 causes the memory cells in the arrays 20, 22 to be periodically refreshed. These command signals, and the manner in which they accomplish their respective functions, are conventional. Therefore, in the interest of brevity, a further explanation of these control signals will be omitted.
Each of the memory arrays 20, 22 contains a large number of memory cells arranged in rows and columns, each of which stores a bit of data. In a DRAM, the memory cells are implemented with respective capacitors. However, charge gradually leaks from a memory cell capacitor, thus making it necessary to periodically recharge the capacitor, which is a procedure known as a refresh of the memory cell. Memory cells are normally refreshed by periodically activating a row of memory cells, thereby coupling each memory cell in the activated row to a respective sense amplifier. The sense amplifier senses the voltage to which each memory cell was initially charged, and then charges or discharges each memory cell to the initial voltage.
A variety of techniques have been devised to refresh the memory cells of DRAMs. In some modes, the rows of memory cells that are to be refreshed are selected by applying corresponding row addresses to the DRAM. As mentioned above, in the self-refresh mode of operation, the addresses of rows that are to be refreshed are generated by circuitry internal to the DRAM in response to receipt of the self refresh command. In all cases, the refresh is controlled by the refresh controller 30.
A block diagram of a portion of a typical prior art refresh controller 100 and a portion of a typical row address driver 102 are shown in FIG. 2. The refresh controller 100 may be used in the refresh controller 30 in the SDRAM of FIG. 1, and the row address driver 102 may be used in the row decoder 28 in the SDRAM 10 of FIG. 1. It will be understood that the refresh controller 100 and the row address driver 102 each include a large number of additional elements that have been omitted from FIG. 2 in the interest of brevity. The refresh controller 100 includes an oscillator 104 that generates a periodic signal, as is well known in the art. The periodic signal from the oscillator 104 is applied to a clock input of a binary counter 108. In the embodiment explained herein, the counter has 9 stages, and thus outputs 9 row address bits RA0-RA8 arranged from the least significant bit RA0 to the most significant bit RA8. However, it will be understood that a large or smaller number of address bits may be generated by the counter 108 depending upon the number of rows in the array. The output of the counter 108 is applied to one set of inputs to the multiplexer 18 (see, also, FIG. 1). A second set of inputs to the multiplexer 18 is coupled to the address bus 14 (FIG. 1) through the address register 12 to receive a second set of row address bits RA0-RA8. In the self-refresh mode, an REF input to the multiplexer 18 from the command decoder 68 (FIG. 1) causes the multiplexer 18 to select the row address bits RA0-RA8 from the counter 108 and apply them to the row address driver 102 (FIG. 1).
The row address driver 102 includes a row pre-decoder 114 that receives the row address bits RA0-RA8 from the multiplexer 18 and outputs pre-decoded row address signals, RA0 less than 0:1 greater than , RA12 less than 0:3 greater than , RA34 less than 0:3 greater than , and RA56 less than 0:3 greater than based on various combinations of the row addresses RA0-RA8. The row address signals RA0 less than 0:1 greater than  consists of two signals RA less than 0 greater than  and RA less than 1 greater than  that correspond to the binary values of RA0. More specifically, when the address bit RA0 is low, RA less than 0 greater than  is high and RA less than 1 greater than  is low. When the address bit RA0 is high, RA less than 0 greater than  is low and RA less than 1 greater than  is high. The other pre-decoded row address signals are generated in a similar manner, except that two adjacent row address bits are decoded together. For example, RA34 less than 0:3 greater than  correspond to the binary values of RA3 and RA4 as shown in Table 1 below:
The remaining pre-decoded row address signals RA12 less than 0:3 greater than , RA56 less than 0:3 greater than and RA78 less than 0:3 greater than  are generated in the same manner.
The pre-decoded row address signals are coupled through a set of 18 pass gates 120 that are controlled by an equilibrate signal EQ and its compliment, which is generated by an inverter 124. However, it will be understood that logic gates other than the pass gates 120 may be used to selectively output the pre-decoded row address signals. The EQ signal may be generated by the command decoder 68 (FIG. 1). When the EQ signal is active high during equilibration of the arrays 20, 22, the pass gates 120 are disabled so that the pre-decoded row address signals are not coupled to the arrays 20, 22. Instead, the pre-decoded row address signals are shunted to ground by an NMOS transistor 126 being turned ON by the high EQ signal. When the EQ signal is inactive low, the transistor 126 is turned OFF and the pass gates 120 are enabled to couple the pre-decoded row address signals to the arrays 20, 22. Thus, the pre-decoded row address signals switch from inactive to active states for refresh, and then back to inactive states after each row is refreshed.
The RA78 less than 0:3 greater than  pre-decoded row address signals are used to generate phase signals LPH* less than 0:3 greater than  at the output of a set of inverters 126. The LPH* less than 0:3 greater than  signals are thus simply the inverse of the RA78 less than 0:3 greater than  signals, and they are active low. As explained further below, the LPH* less than 0:3 greater than  signals are used select one of four sets of phases of row address decoders in the arrays 20, 22.
The topography of one of the memory arrays 20, including the routing of the phase signals LPH* less than 0:3 greater than  and the pre-decoded row address signals RA0 less than 0:1 greater than  RA12 less than 0:3 greater than , RA34 less than 0:3 greater than  and RA56 less than 0:3 greater than  through the array 20, is shown in FIG. 3. The array 20 includes a plurality of sub-arrays 300, each of which is surrounded by an even set of row decoders RD-E, an odd set of row decoders RD-O, both of which are included in the row decoder 28 of FIG. 1, and two sets of sense amplifiers SA, which are included in the sense amplifiers and associated column circuitry 50, 52 of FIG. 1. As is well known in the art, even numbered word lines extend through the sub-arrays 300 from the even row decoders RD-E, odd numbered word lines extend through the sub-arrays 300 from the odd row decoders RD-O, and complimentary pairs of digit lines extend through the sub-arrays 300 from the sense amplifiers SA.
A set of row decoders RD-E and RD-0 for one of the sub-arrays 300 is shown in greater detail in FIG. 4. Each even row decoder RD-E and each odd row decoder RD-O includes 4 identical decoder circuits 310 labeled DEC0-DEC3, respectively. The pre-decoded row address signals RA12 less than 0:3 greater than , RA34 less than 0:3 greater than , and RA56 less than 0:3 greater than  are coupled to the even row decoders 310E0-3 through a first set of drivers 312 that are enabled by the even RA0 bit, RA0 less than 0 greater than . Similarly, pre-decoded row address signals RA12 less than 0:3 greater than , RA34 less than 0:3 greater than , and RA56 less than 0:3 greater than  are coupled to the odd row decoders 310O0-3 through a second set of drivers 314 that are enabled by the odd RA0 bit, RA0 less than 1 greater than . When any of the drivers are not enabled, its output is biased low so that the row address signals RA12 less than 0:3 greater than , RA34 less than 0:3 greater than , and RA56 less than 0:3 greater than  are all low. Thus, depending on the state of the RA0 signals, either all of the even row decoders 310E0-3 are enabled or all of the odd row decoders 310O0-3 are enabled. However, if RA0 less than 0 greater than  and RA0 less than 1 greater than  are both low, neither the even row decoders 310E0-3 nor the odd row decoders 310O0-3 are enabled.
Each of the decoder circuits 310 for both the even and odd word lines also receive the pre-decoded row address signals RA12 less than 0:3 greater than , RA34 less than 0:3 greater than , and RA56 less than 0:3 greater than . However, each of the decoder circuits 310 is enabled by a respective phase signal LPH* less than 0:3 greater than . Thus, for example, the decoder circuits 310E2 and 310O2 are enabled by LPH* less than 2 greater than  being high. However, only the decoder circuits driving the even word lines will be enabled if RA less than 0 greater than  is high, and only the decoder circuits driving the odd word lines will be enabled if RA less than 1 greater than  is high. Thus, if LPH* less than 2 greater than  and RA less than 0 greater than  are both high, only the decoder circuit 310E2 will be enabled.
One embodiment of the decoder circuit 310 is shown in FIG. 5. Each decoder circuit 310 includes 4 RA56 decoder circuits 320 (only one is shown in FIG. 5), although each of the RA56 decoder circuits 320 receives a respective one of four different RA56 less than 0:3 greater than  signals. Similarly, each RA56 decoder circuit 320 includes 4 RA34 decoder circuits 326 (only one is shown in FIG. 5), and each RA34 decoder circuit 326 receives a respective one of four different RA34 less than 0:3 greater than  signals. Finally, each RA34 decoder circuit 326 includes 4 RA12 decoder circuits 330 (only one is shown in FIG. 5), and each RA12 decoder circuit 330 receives a respective one of four different RA12 less than 0:3 greater than  signals. Thus, each decoder circuit 310 includes 4 RA56 decoder circuits 320, 16 RA34 decoder circuits 326, and 64 RA12 decoder circuits 330. Each of the decoder circuits 320, 326, 330 also receive one of the phase signals LPH* to enable the decoder circuit when the received LPH* signal is active low.
Each RA56 decoder circuit 320 includes an NMOS pass transistor 340 that is enabled when the RA56 input is high. When enabled, the transistor 340 couples node 342 to the LPH* signal, which will be low when the RA56 decoder is active. The low LPH* signal also turns OFF an NMOS transistor 346. Thus, if the RA56 input is high and the LPH* input is low, the voltage at the node 342 will be low. Finally, if the LPH* input is high, the node 342 will be precharged high through the transistor 346 regardless of the state of the RA56 input.
The RA34 decoder circuit 326 includes similar structure and operates in a similar manner. More specifically, the RA34 decoder includes an NMOS pass transistor 350 and an NMOS shunting transistor, both of which are coupled to node 356. If the decoder circuit is disabled by LPH* being inactive high, the node 356 will be high. The transistor 350 couples the node 356 to the node 342 if the RA34 input is high, and isolates the node 342 from the node 342 if the RA34 input is low. Thus, if the decoder is enabled by LPH* being low and RA56 and RA34 are both high, the node 356 will be low.
The RA12 decoder 330 also includes an NMOS pass transistor 360, which is turned ON by RA12 being high. If RA12 is high, node 356 is coupled to the gate of an NMOS transistor 362 and to the gate of a PMOS transistor 364 through an NMOS transistor 368 that is biased ON by a pumped voltage Vccp. Thus, the transistors 362, 364 essentially function as an inverter that drives a word line WL.
If the decoder circuit 310 is initially inactive by LPH* being high, the word line WL is grounded through an NMOS shunting transistor 370. If LPH* subsequently transitions active low, the word line WL remains latched because the low WL voltage turns ON a PMOS transistor 374, thereby turning OFF the PMOS transistor 364 and turning ON the NMOS transistor 362 through the transistor 368. Thus, the initial condition of the decoder circuit 310 will latch the word line WL low.
If LPH* is active low, and all of the pre-decoded addresses RA56, RA34 and RA12 are all high, the low LPH* signal will be coupled through all of the pass transistors 340, 350, 360 to the gate of the PMOS transistor 364 and the gate of the NMOS transistor 362. The NMOS transistor 362 will then be turned OFF and the PMOS transistor 364 will be turned ON to drive the word line WL high. Thus, the decoder circuit 310 will drive a word line WL to which it is connected high only if the decoder circuit 310 is enabled by an active low LPH* signal and all of the pre-decoded address signals RA coupled to the decoder circuit 310 are high.
Returning to FIG. 3, it will be apparent that the signal lines carrying the re-decoded row address signals and the phase signals are relatively long since they must extend across the entire array 20. In fact, the lines carrying these signals must extend across the entire array 20 several times because they must be applied to all of the row decoders RD. It requires a significant amount of power to switch the state of a signal line because current must be provided to charge and discharge the capacitance of the line, and this current must flow through switching devices, such as MOSFET transistors (not shown), that have appreciable resistance. The amount of current needed to charge the capacitance of the lines carrying the pre-decoded row address signals and the phase signals is proportional to the length of the line. The power required to switch the signal lines carrying the row address and phase signals is relatively high because they are relatively long. Further, since the pre-decoded row address signals and the phase signals switch after each row is precharged, the self-refresh mode of conventional DRAMs requires a great deal of power. The large amount of power required reduces the operating time of battery powered computers using such DRAMs.
Therefore, there is a need for DRAMs that can operate in a self refresh mode while consuming a relatively little amount of power. It would also be desirable to do so without extensively redesigning conventional refresh controllers that cause DRAMs to consume a great deal of power in the self-refresh mode.
A method and apparatus for refreshing an array of memory cells in a dynamic random access memory is adapted to require relatively little power when operating in a self-refresh mode. In accordance with one aspect of the invention, a gray code counter is used to generate a sequence of row addresses so that only one bit of the address changes from one row address to the next row address in the sequence. Since only one bit of the row address changes each refresh cycle, only one row address line extending through the memory array must be switched each refresh cycle, thereby requiring relatively little power. In another aspect of the invention, a row pre-decoder continuously couples at least some of the row address bits to the row decoders from one refresh cycle to the next so that at least some of the row address row address lines extending through the memory array need not be switched from one refresh cycle to the next. Again, avoiding the switching of such lines minimizes the power required in the self-refresh mode of operation.